1. Field of the Invention
The present invention relates to methods and circuitry for generating ramped voltage signals having controlled maximum amplitude, without use of a comparator. In preferred embodiments, the invention is a switching controller which generates at least one ramped voltage signal (for use in generating at least one pulse width modulated power switch control signal for a DC-to-DC converter) such that each ramped voltage signal has a controlled maximum amplitude.
2. Description of the Related Art
In power supply circuitry, it is often desired to produce a ramped voltage or multiple, parallel channels of ramped voltages. For example, in some DC-to-DC converters (sometimes referred to as interleaved PWM DC-to-DC converters, where xe2x80x9cPWM xe2x80x9d denotes xe2x80x9cpulse width modulatedxe2x80x9d), multiple channels of ramped voltages are provided to comparator circuitry for use in generating power switch control signals for controlling the duty cycle of each power switch of the DC-DC converter and thus the amplitude of the DC output voltage. The waveforms and maximum amplitudes of the ramped voltages are identical (to the extent practical) except that each has a different phase than the others.
More generally, circuitry providing ramped voltage signals with controlled maximum amplitude is useful for a wide variety of applications, including but not limited to interleaved PWM DC-to-DC converter applications. However, when implementing such circuitry (especially when implementing it as an integrated circuit or part of an integrated circuit), process and temperature variations typically cause variations in the characteristics (e.g., maximum amplitude) of the ramped voltages.
FIG. 1 is a conventional DC-to-DC converter which includes current mode switching controller 1 implemented as an integrated circuit, and boost converter circuitry which is external to controller chip 1. The boost converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor Rs, Schottky diode D, capacitor Cout, feedback resistor divider RF1, and RF2, compensation resistor Rc, and compensation capacitor Cc, connected as shown. The FIG. 1 circuit produces a regulated DC output voltage Vout across load Ro, in response to input DC voltage Vin.
Controller chip 1 includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an output potential VDR at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having xe2x80x9cset xe2x80x9d terminal coupled to oscillator 2, xe2x80x9creset xe2x80x9d terminal coupled to the output of comparator 8, and an output coupled to the input of driver 6), error amplifier 7 (having a non-inverting input maintained at reference potential Vref), and circuit 9 (having a first input coupled to the second output of oscillator 2, a second input coupled to pad 13, and an output coupled to the inverting input of comparator 8).
Pad 13 is at potential Vc, which is determined by the output of error amplifier 7 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential Vref) and the values of external resistor Rc and capacitor Cc. Reference potential Vref is set (in a well known manner) by circuitry within chip 1, and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage Vout, resistors RF1, and RF2 with the appropriate resistance ratio RF1/RF2 are employed.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positivegoing leading edge of this pulse train sets latch 4. Each time latch 4 is set, the potential VDR asserted by driver 6 to the gate of transistor N1 causes transistor N1 to turn on, which in turn causes current IL from the source of N1 to increase in ramped fashion (more specifically, the current IL increases as a ramp when transistor N1 is on, and is zero when transistor N1 is off. The current through diode D is zero when N1 is on, it increases sharply when N1 switches from on to off, then falls as a ramp while N1 is off, and then decreases sharply to zero when N1 switches from off to on). Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential Rref and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train.
Oscillator 2 asserts ramped voltage VR (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. Circuit 9 asserts the potential Vcxe2x88x92VR to the inverting input of comparator 8. Assertion of the potential Vcxe2x88x92VR (rather than Vc) to comparator 8 is necessary for stability.
The non-inverting input of comparator 8 is at potential Vs=ILRs, which increases in ramped fashion in response to each xe2x80x9cset xe2x80x9d of latch 4 by oscillator 2. When Vs=Vcxe2x88x92VR (after latch 4 has been set), the output of comparator 8 resets latch 4, which in turn causes the potential VDR asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by the described use of both of the signals output from oscillator 2 and feedback asserted to error amplifier 7 from Node A, controller chip 1 switches transistor N1 on and off with timing that regulates the output potential Vout of the FIG. 1 circuit.
FIG. 2 is a diagram of a conventional circuit for generating a ramped voltage VR of the type mentioned with reference to FIG. 1. In the FIG. 2 circuit, which is typically implemented as part of a controller chip, the voltage across capacitor CT is the ramped voltage VR. The voltage across capacitor CT increases while switch Q1 (implemented as a transistor) is open (i.e., when no current flows through the channel of Q1), as current flows from the top rail through resistor RT to the top plate of the capacitor, and decreases rapidly when switch Q1 is closed to cause capacitor CT to discharge. Comparator 16 compares the output potential VR with a first reference potential Ref1, and asserts a xe2x80x9creset xe2x80x9d signal to latch 15 when the output potential rises to the first reference potential Ref1. In response to the reset signal, latch 15 asserts a control signal which causes switch Q1 to enter its closed state. A second comparator 17 compares the output potential VR with a second reference potential Ref2 (which is lower than reference potential Ref1), and asserts a xe2x80x9cset xe2x80x9d signal to latch 15 when the output potential falls to the second reference potential Ref2. In response to the set signal, latch 15 asserts a control signal which causes switch Q1 to enter its open state.
However, the conventional circuit of FIG. 2 has a number of disadvantages and limitations, including the following:
large (in terms of area on the controller chip) and complex circuitry is required to implement each of its comparators (comparators 16 and 17). Even larger and more complex circuitry is required to implement a larger number of comparators in DC-to-DC converters having multiple power channels, in which each of multiple channels has a set of one or more comparators for use in generating a ramped voltage;
to generate ramped voltage VR with a very high frequency (very short period), it may be necessary to implement each comparator to have low propagation delay (e.g., in the range from 10 nsec to 15 nsec), which necessitates high performance, high quiescent current comparator designs; and
due to use of the comparators (comparators 16 and 17), the ramped voltage VR has a frequency dependent offset. It is difficult to compensate for the nonlinear variation (with frequency) of the characteristics of ramped voltage VR, and it may be impractical to implement the controller to be capable generating ramped voltage VR with a very high frequency.
The ramped generation circuit of the invention is useful to replace the circuitry within oscillator circuit 2 of FIG. 1 for generating ramped voltage VR(which circuitry can have the design of FIG. 2).
U.S. patent application Ser. No. 09/231,046, filed Jan. 14, 1999 and assigned to the assignee of the present invention, discloses ramped voltage generation circuitry for use in a current mode switching controller for a DC-to-DC converter having multiple channels. The ramped voltage generation circuitry generates multiple ramped voltages, each having a different phase. The maximum amplitude of each ramped voltage is controlled in the following manner to be uniform. In response to a clock signal (one clock signal per channel), ramped voltage generating capacitors (one for each channel) are periodically charged and discharged. In the disclosed embodiment, each clock signal is generated using logic circuitry, a clock generation capacitor, and a comparator. In each channel, a feedback loop (comprising an amplifier, capacitor, transistor, and current mirror) controls the rate at which the ramped voltage generating capacitor charges, using feedback (which is provided to the feedback loop during a short interval of time immediately before the ramped voltage generating capacitor discharges) indicative of the voltage across the ramped voltage generating capacitor. Although each ramped voltage generating capacitor charges periodically and discharges periodically, the feedback tends to move the level of each ramped voltage signal toward a desired maximum amplitude (during the short interval of time just before the ramped voltage generating capacitor discharges). However, use of clock signal generation circuitry including a comparator in this ramped voltage generation circuit has disadvantages and limitations including those mentioned above (the clock signal generating circuitry is large in terms of area on the controller chip, complex circuitry is required to implement the comparator with high performance, high quiescent current characteristics (where the clock must have very high frequency), and use of a comparator in the clock signal generating circuitry may cause it to be impractical to implement the controller to be capable of generating ramped voltages having very high frequency).
U.S. patent application Ser. No. 09/365,968, filed Aug. 2, 1999 (assigned to the assignee of the present invention), also discloses a ramped voltage generation circuit for use in a current mode switching controller for a DC-to-DC converter. The ramped voltage generation circuit employs a clock signal to periodically charge and discharge a ramped voltage generating capacitor, and a feedback loop (comprising an amplifier, capacitor, transistor, and current mirror) to control the rate at which the ramped voltage generating capacitor charges. U.S. application Ser. No. 09/365,968 does not disclose circuitry for generating the clock signal.
In a class of embodiments, the invention is a circuit for generating at least one ramped voltage for use in a switching controller for a DC-to-DC converter, and a method for generating such a ramped voltage without use of any comparator. The ramped voltage generation circuit generates a ramped voltage signal having controlled maximum amplitude without use of a comparator. The ramped voltage is a voltage developed across a periodically charged (and discharged) capacitor, or optionally a level-shifted version of such a voltage. In a class of preferred embodiments, the inventive circuit includes a ring oscillator which generates a clock signal (without use of a comparator) for use in controlling the periodic charging and discharging of the capacitor, and a feedback loop which generates a supplemental charging current for the capacitor (in response to feedback indicative of the ramped output voltage). Preferably, the ring oscillator is a current-starved ring oscillator biased at a potential generated using a zero temperature coefficient bias current source, and generates the clock with a frequency that is (or is nearly) temperature invariant. Preferably, the feedback loop includes a sample-adjust-hold circuit which samples the ramped output voltage shortly before the capacitor discharges and generates an adjustment voltage indicative of the difference between a reference voltage and the sampled output voltage (and holds the adjustment voltage for use in the next charging cycle). Thus, feedback is employed to control the ramped output voltage so that its maximum value matches the reference voltage. Preferably, a current mirror generates the supplemental charging current in response to the adjustment voltage held by the sample-adjust-hold circuit.
Elimination of comparators (in accordance with the invention) from a ramped voltage generation circuit overcomes the noted disadvantages and limitations of conventional ramped voltage generation circuits, and saves silicon area (in integrated circuit implementations). In accordance with the invention, a switching controller which generates at least one ramped voltage signal (for use in generating a pulse width modulated power switch control signal for a DC-to-DC converter) can be implemented in a manner consuming less area for the same ramped voltage frequency (than a conventional circuit employing at least one comparator), with the peak and valley levels of the ramped voltage being invariant to process and temperature variations, and with reduced supply voltage (Vdd).
The invention can be implemented as a portion of a switching controller chip (integrated circuit) which generates one or more ramped voltage signals (each for use in generating a pulse width modulated power switch control signal for a DC-to-DC converter) such that each ramped voltage signal has a controlled maximum amplitude.